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r 5112 s series 42 v input ultra l o w supply current vr with reset no.ea - 406 - 160420 1 outline r5112s is a n ultra - low supply current voltage regulator with a voltage detector featuring 200 ma output current and 42 v input voltage. this device consists of an output short - circuit protection circuit, an over current protection circuit, and a thermal shutdown circuit in addition to the basic regulator circuits. the operating temperature range is between ? 40 c to 1 0 5 c, and the maximum input voltage is 42 v. the output voltages are internally fixed at either of the following: 1.8 v, 2.5 v, 2.8 v, 3.0 v, 3.3 v, 3.4 v, or 5.0 v . th e output voltage accuracy is 0.6 % . the detector threshold accuracy of the voltage detector is 0.6 % . this device is offered in an 8 - pin hsop - 8e package with high power dissipation . features input voltage range (maximum rating) 3.5 v to 42 v (50 v) operating temperature range ? 40 c to 1 0 5 c (usable in high - temperature environment) supply current typ. 3 . 8 a standby current typ. 0.1 a dropout voltage typ. 0.6 v (i out = 200 ma, v set = 5.0 v) output voltage range 1.8 v / 2.5 v / 2.8 v / 3.0 v / 3.3 v / 3.4 v / 5.0 v *contact ricoh sales representatives for other voltages. output voltage accuracy 0.6 % (ta = 25 c) output voltage temperature - drift coefficient typ. 60 ppm/ c detector threshold range r5112sxx1b: 1.6 v to 4.8 v r5112sxx1d: 2.9 v to 4.8 v detector threshold accuracy 0.6 % ( ta = 25 c ) detector threshold temperature coefficient typ. 60 ppm/ c line regulation typ. 0.0 1 %/v (2.5 v v set : v set + 1 v v in 42 v ) built - in output short - circuit protection circuit typ. 8 0 ma built - in overcurrent protection circuit typ. 3 5 0 ma built - in thermal shutdown circuit thermal shutdown temperature: typ. 1 7 0 c ceramic capacitors are recommended to be used with this device c out = 0 .1 f or more package hsop - 8 e applications power source for home appliances such as refrigerators, rice cookers, and electric hot - water pot . power source for notebook pcs, digital tvs, cordless phones, and private lan system. power source for office equipment machines such as copiers, printers, facsimiles, scanners , and projectors .
r5 1 1 2 s no.ea - 406 - 160420 2 selection guide the set output voltage is user - selectable. product name package quantity per reel pb free halogen free r5112sxx1 ? - e2 - fe hsop - 8 e 1,000 pcs yes yes xx: specify the set output voltage (v set ) and the set detector threshold ( ? v set ) by using serial numbers starting from 01. ( 1 ) ? : select the voltage detection type from the following b : sense pin detection d: v out pin detection (1) the combinations of v set and ? v set are the following three conditions. sense pin detection: v set = 3.3 v to 5.0 v , ? v set = 2.5 v to 5.0 v sense pin detection: v set = 1.8 v to 3.2 v , ? v set = 1.6 v to 2.9 v v out pin detection: v set = 3.3 v to 5.0 v , ? v set = 2.9 v to 5.0 v
r5 1 1 2 s no.ea - 406 - 160420 3 block diagram s r5 1 12sxxxb ( sense p in d etection ) v dd d out c d v out ce gnd on/off circuit t hermal shut down current limit sense r5112sxxx d (v out p in d etection) v dd d out c d v out ce gnd on/off circuit t hermal shut down current limit
r5 1 1 2 s no.ea - 406 - 160420 4 pin descriptions hsop - 8e top view bottom view 5 8 6 4 2 1 3 8 6 5 7 1 3 4 2 7 (1) 1 hsop - 8e (r511 2 sxxx b / d ) pin no . symbo l description 1 v dd input pin 2 ce chip enable pin (active - high) 3 nc no connection 4 d out ( 2 ) v d output pin ( nch open drain) 5 c d pin for setting vd release output delay time ( power - on reset time ) 6 sense vd voltage sense pin (r5112sxxxb) nc no connection (r5112sxxxd) 7 gnd ground pin 8 v out output pin (1) the tab on the bottom of the package enhances thermal performance and is electrically connected to gnd (substrate level). the tab is recommended to connect to the ground plane on the board. otherwise it may be left floating. (2) d out p in should be pull ed- u p to an external voltage level.
r5 1 1 2 s no.ea - 406 - 160420 5 pin equivalent circuit diagrams v out pin ce pin v out driver ce c d pin d out pin c d driver d out driver sense pin sense
r5 1 1 2 s no.ea - 406 - 160420 6 absolute maximum ratings symbol item rating unit v in input voltage ? 0.3 to 50 v peak input voltage ( 1 ) 60 v v ce input voltage ( ce pin) ? ? ? ? 0.3 to 7.0 v v sen s e sense pin input voltage ? ? ? absolute maximum ratings electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent damages and may degrade the lifetime and safety for both device and system using the device in the field. the functional operation at or over these absolute maximum ratings are not assured. recommended operating conditions symbol item rating unit v in input voltage 3.5 to 42 v v ce input voltage ( ce pin) 0 to 42 v v dout d out pin output voltage 0 to 5.5 v v sense sense pin input voltage 0 to 5.5 v ta operating temperature ? recommended operating conditions all of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. the semiconductor devices cannot operate normally over the recommended operating conditions, even if when they are used over such conditions by momentary electronic noise or surge. and the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions. (1) duration time: 200 ms (2) refer to p ower dissipation for detailed information.
r5 1 1 2 s no.ea - 406 - 160420 7 electrical characteristics c in = c out = 0.1 f , v in = 14 v , unless otherwise noted. the specifications surrounded by are guaranteed by design e ngineering at ? 40c ta 10 5c . r51 12 sxxxx - fe for all (t a = 25c) symbol item conditions min. typ. max. unit i ss supply current i out = 0 ma 3 . 8 9.8 a istandby standby current v in = 42 v , v ce = 0 v 0.1 1 .0 a i pd ce pull - down current 0.2 0.6 a v ceh ce input voltage "h" 2.2 42 v v cel ce input voltage "l" 0 1.0 v all test items listed under electrical characteristics are done under the pulse load condition (tj ta = 25 c) . vr (t a = 25c) symbol item conditions min. typ. max. unit v out output voltage v set + 1 v v in 42 v (v set < 2.5 v : v set + 1 v = 3.5 v), i out = 1 ma ta = 25 c 0.99 4 1.0 06 v ? 40c ta 1 0 5 c 0.98 4 1.0 16 ? v out / ? i out load regulation v in = v set + 3 .0 v 1 ma i out 200 ma ? 1 0 0 4 0 mv v dif dropout voltage i out = 200 ma v set < 2.5 v 1.6 2.5 v 2.5 v v set < 3.3 v 1.2 2.2 3.3 v v set < 5.0 v 0. 8 2.0 v set = 5.0 v 0.6 1.2 ? ? v in 42 v (v set < 2.5 v : v set + 1 v = 3.5 v), i out = 1 ma ? 0.02 0.01 0.02 %/v i lim output current limit v in = v set + 3.0 v 2 2 0 3 5 0 420 ma i sc short current limit v out = 0 v 6 0 80 11 0 ma t tsd thermal shutdown temperature junction temperature 1 7 0 c t tsr thermal shutdown release temperature junction temperature 135 c all test items listed under electrical characteristics are done under the pulse load condition (tj ta = 25 c) .
r5 1 1 2 s no.ea - 406 - 160420 8 c in = c out = 0.1 f , v in = 14 v , unless otherwise noted. the specifications surrounded by are guaranteed by design e ngineering at ? 40c ta 10 5c . vd (t a = 25c) symbol item conditions min. typ. max. unit ? v det detector threshold v dd = v out (vout detection ) ta = 25 c 0.9 9 4 1.006 v ? 40 c ta 1 0 5 c 0.984 1.016 v hys detector threshold hysteresis ? v det 0.011 ? v det 0.018 ? v det 0.025 v tde lay release output delay time (power - on reset) c d = 10 nf 3 6 15 ms v dout d out pull - up voltage 5.5 v i outdout nch. output current (d out output pin) v in = 3.5 v, v dout = 0.1 v 1.0 2.6 ma i leakdout nch. leakage current (d out output pin) v dout = 5.5 v 0.3 a r lcd c d pin discharge nch tr.on resistance v ce = 0 v, v cd = 0.1 v 12 30 k r sense sense resistance 2 50 m all test items listed under electrical characteristics are done under the pulse load condition (tj ta = 25 c) .
r5 1 1 2 s no.ea - 406 - 160420 9 product - specific electrical characteristics r5112sxxxb - fe (t a = 25c) product name v out [ v ] v de t [ v ] v hys [v] ta = 25c ? 40 c ta 1 0 5 c ta = 25c ? 40 c ta 1 0 5 c min. typ. max. min. max. min. typ. max. min. max. min. max. r5112x011b 4.970 5.000 5.030 4.920 5.080 4.573 4.600 4.627 4.527 4.674 0.050 0.117 r5112x021b 1.790 1.800 1.810 1.772 1.829 1.590 1.600 1.610 1.574 1.626 0.017 0.041 r5112x031b 4.970 5.000 5.030 4.920 5.080 4.473 4.500 4.527 4.428 4.572 0.049 0.115 r5112x041b 4.970 5.000 5.030 4.920 5.080 4.374 4.400 4.426 4.330 4.470 0.048 0.112 r5112x051b 4.970 5.000 5.030 4.920 5.080 4.274 4.300 4.326 4.231 4.369 0.047 0.110 r5112x061b 4.970 5.000 5.030 4.920 5.080 4.175 4.200 4.225 4.133 4.267 0.045 0.107 r5112x071b 4.970 5.000 5.030 4.920 5.080 3.678 3.700 3.722 3.641 3.759 0.040 0.094 r5112x081b 3.281 3.300 3.319 3.248 3.353 2.982 3.000 3.018 2.952 3.048 0.032 0.077 r5112x091b 3.281 3.300 3.319 3.248 3.353 2.883 2.900 2.917 2.854 2.946 0.031 0.074 r5112x101b 3.281 3.300 3.319 3.248 3.353 2.783 2.800 2.817 2.755 2.845 0.030 0.071 r5112x111b 3.281 3.300 3.319 3.248 3.353 2.684 2.700 2.716 2.657 2.743 0.029 0.069 r5112x121b 4.970 5.000 5.030 4.920 5.080 4.075 4.100 4.125 4.034 4.166 0.044 0.105 r5112x131b 3.380 3.400 3.420 3.346 3.454 3.081 3.100 3.119 3.050 3.150 0.034 0.079 r5112x141b 3.281 3.300 3.319 3.248 3.353 3.081 3.100 3.119 3.050 3.150 0.034 0.079 r5112sxxxd - fe (t a = 25c) product name v out [ v ] v de t [ v ] v hys [v] ta = 25c ? 40 c ta 1 0 5 c ta = 25c ? 40 c ta 1 0 5 c min. typ. max. min. max. min. typ. max. min. max. min. max. r5112x011d 4.970 5.000 5.030 4.920 5.080 4.573 4.600 4.627 4.527 4.674 0.068 0.117 r5112x031d 4.970 5.000 5.030 4.920 5.080 4.473 4.500 4.527 4.428 4.572 0.066 0.115 r5112x041d 4.970 5.000 5.030 4.920 5.080 4.374 4.400 4.426 4.330 4.470 0.065 0.112 R5112X051D 4.970 5.000 5.030 4.920 5.080 4.274 4.300 4.326 4.231 4.369 0.063 0.110 r5112x061d 4.970 5.000 5.030 4.920 5.080 4.175 4.200 4.225 4.133 4.267 0.062 0.107 r5112x071d 4.970 5.000 5.030 4.920 5.080 3.678 3.700 3.722 3.641 3.759 0.054 0.094 r5112x081d 3.281 3.300 3.319 3.248 3.353 2.982 3.000 3.018 2.952 3.048 0.044 0.077 r5112x091d 3.281 3.300 3.319 3.248 3.353 2.883 2.900 2.917 2.854 2.946 0.043 0.074 r5112x121d 4.970 5.000 5.030 4.920 5.080 4.075 4.100 4.125 4.034 4.166 0.060 0.105 r5112x131d 3.380 3.400 3.420 3.346 3.454 3.081 3.100 3.119 3.050 3.150 0.046 0.079 r5112x141d 3.281 3.300 3.319 3.248 3.353 3.081 3.100 3.119 3.050 3.150 0.046 0.079
r5 1 1 2 s no.ea - 406 - 160420 10 theory of operation (2) (1) (3) (4) (3) v in v out /vsense v cd v dout +v det - v det t delay t delay v tcd (1) when the v out pin voltage (v out ) /sense pin voltage (v sense ) become s more than the release voltage (+v det ), the d out pin voltage (v dout ) becomes ? h ? a fter the release output delay time ( tdelay ) . (2) when the detect output delay time i s 25 s (typ.) or less even if v out / v sense becomes lower than the detector threshold ( ? v det ), t he voltage detector (vd) does not go into the detecting state. (3) when v out / v sense become s lower than ? v det , v dout becomes "l" a fter the detect output delay time ( t phl , typ. 25 s ) and the vd goes into the detecting state. (4) when v out / v sense become s more than +v det , v dout becomes " h " a fter the release output delay time (v tcd = typ. 0.73 v) . r5112sxx xb/d vd timing chart
r5 1 1 2 s no.ea - 406 - 160420 11 delay operation and released output delay time (tdelay) c d pin threshold voltage ( v tcd ) released voltage ( +v det ) gnd gnd detector voltage ( - v det ) detect output delay time ( t phl ) release output delay time ( t delay ) v out / sense pin c d pin voltage d out pin released output delay timing diagram when the operating voltage higher than the released voltage is applied to v out pin ( r511 2 sxxxd ) or sense pin ( r511 2 s x x xb ) , charge to an external capacitor starts, then c d pin voltage (v cd ) increases. d out pin ( r511 2 sx xxb /d ) ma intains the released output until v cd reaches the threshold voltage of the release output delay pin (v tcd ). and when v cd is over v tcd , d out pin is inverted from ? l ? to ? h ? . that is, the charged external capacitor starts discharging. when the operating voltage lower than the detector threshold is applied to v out pin / sense pin , the detect output delay time, which is the time until the output voltage is inverted from ? h ? to ? l ? , remains constant independent of the external capacitor. released output delay time released output delay time (tdelay) is determined by the following formula. c d (f) represents capacitance of the external capacitor tdelay (s ) = 0.73 c d (f) / (1. 2 10 -6 ) u se 100 pf or higher c d w hen allowing this device to detect vout/sense pin de creasing slower than 0.1 v/s . released output delay time indicates the time between the instance when v out pin ( r511 2 sxx xd ) or sense pin ( r511 2 sxxx b ) shifts from ?1. 5 v? to ? ? v det + 2 .0 v? by the application of a pulse voltage and the instance when the output voltage reaches 2.5 v after pulled up d out pin ( r511 2 sxx x b /d ) to 5.0 v with a resistor of 100 k ? . - v det +
r5 1 1 2 s no.ea - 406 - 160420 12 voltage setting (r511 2 sxx xb/d ) vd detects the drop of the vr output voltage (v out ). when the vd release voltage (+v det ) is set to a voltage above the vr output voltage, the reset signal of vd is not released even if vd monitors the vr output voltage returns to the normal value after detecting the drop of vr. to prevent this issue, the following condition is required betwe en v out and +v det. ( vr set output voltage ) x 0.984 ? 4 0 mv > ( vd set detector threshold ) x 1.0 16 x 1.0 25 when using a device with out the above conditions of v out and +v det , careful consideration must be given to the system operation before use.
r5 1 1 2 s no.ea - 406 - 160420 13 application information typical applications r 511 2 s xx xb v dd v out ce c 1 c 2 gnd c d c d sense dout r1 v cc microprocessor reset v in r 5112sxxx b typical applications r 5112 s xx x d v dd v out ce c 1 c 2 gnd c d c d d out r1 v cc microprocessor reset v in r5112 sxx xd typical applications
r5 1 1 2 s no.ea - 406 - 160420 14 recommended components symbol description c1 (c in ) ceramic capacitor, 0.1 f or more , 50v rated voltage, cga3e3x8r1h104k080ab, tdk c2 (c out ) ceramic capacitor, 0.1 f or more , 50v rated voltage, cga3e3x8r1h104k080ab, tdk c d a capacitor corresponding to setting for release output delay time is required. refer to delay operation and released output delay time (tdelay) in theory of operation for details. r1 a resistor is required to set with consideration of the output current and the leakage current. refer to electrical character istics for details.
r5 1 1 2 s no.ea - 406 - 160420 15 technical notes phase compensation in the r5112s , phase compensation is provided to secure stable operation even when the load current is varied. for this purpose, be sure to use 0.1 f or more of a capacitor ( c 2 ) . in case of using a tantalum type capacitor and the esr (equivalent series resistance ) value of the capacitor is large, the output might be unstable. evaluate the circuit including consideration of frequency characteristics. pcb layout ensure the v dd and gnd lines are sufficiently robust. if their impedance is too high, noise pickup or unstable operation may result. connect 0.1 f or more of the capacitor c1 between the v dd and gnd, and as close as possible to the pins. in addition, connect the capaci tor c2 between v out and gnd, and as close as possible to the pins. prohibited area of the input voltage variation when the input voltage is steeply changed in the following prohibited area, the device may fail to detect or fail to release. variation prohibited area at input voltage ( v in ) falling variation prohibited area at input voltage ( v in ) rising tf gnd v in vp-p tr gnd v in vp-p
r5 1 1 2 s no.ea - 406 - 160420 16 typical characteristics note: typical characteristics are intended to be used as reference data; they are not guaranteed. 1) output v o ltage vs. output current (ta = 25 c) v set = 1.8 v v set = 2.5 v v set = 3.3 v v set = 5.0 v 2) output voltage vs. input voltage (ta = 25 c ) v set = 1.8 v v set = 2.5 v
r5 1 1 2 s no.ea - 406 - 160420 17 v set = 3.3 v v set = 5.0 v 3) supply current vs. temperature v set = 1.8 v v set = 2.5 v v set = 3.3 v v set = 5.0 v
r5 1 1 2 s no.ea - 406 - 160420 18 4) supply current vs. input voltage v set = 1.8 v v set = 2.5 v v set = 3.3 v v set = 5.0 v 5) output voltage vs. temperature v set = 1.8 v v set = 2.5 v
r5 1 1 2 s no.ea - 406 - 160420 19 v set = 3.3 v v set = 5.0 v 6) dropout voltage vs. output current v set = 1.8 v v set = 2.5 v v set = 3.3 v v set = 5.0 v
r5 1 1 2 s no.ea - 406 - 160420 20 7) dropout voltage vs. output v o ltage (ta = 25 c ) 8) ripple rejection vs. input voltage (ta = 25 c , ripple = 0.2 vpp) v set = 1.8 v v set = 2.5 v v set = 3.3 v v set = 5.0 v
r5 1 1 2 s no.ea - 406 - 160420 21 9) ripple rejection vs. frequency (ta = 25 c , ripple = 0.2 vpp ) v set = 1.8 v v set = 2.5 v v set = 3.3 v v set =5.0 v 10) input transient response (ta = 25 c ) v set = 1.8 v v set = 2.5 v 0 2 4 6 8 10 12 0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 -1 0 1 2 3 4 5 6 input voltage v in (v) output voltage v out (v) time (ms) input voltage tr=tf=1s output voltage i out =1ma c 2 = 0.1f c 2 =10f 0 2 4 6 8 10 12 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -1 0 1 2 3 4 5 6 input voltage v in (v) output voltage v out (v) time (ms) input voltage tr=tf=1s output voltage i out =1ma c 2 = 0.1f c 2 =10f
r5 1 1 2 s no.ea - 406 - 160420 22 v set = 3.3 v v set = 5.0 v 11) load transient response (ta = 25 c ) v set = 1.8 v v set = 2.5 v v set = 3.3 v v set = 5.0 v 0 2 4 6 8 10 12 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 6.3 6.8 -1 0 1 2 3 4 5 6 input voltage v in (v) output voltage v out (v) time (ms) input voltage tr=tf=1s output voltage i out =1ma c 2 = 0.1f c 2 =10f 0 2 4 6 8 10 12 14 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 -1 0 1 2 3 4 5 6 input voltage v in (v) output voltage v out (v) time (ms) input voltage tr=tf=1s output voltage i out =1ma c 2 = 0.1f c 2 =10f
r5 1 1 2 s no.ea - 406 - 160420 23 12) ce transient response (ta = 25 c ) v set = 1.8 v v set = 2.5 v v set = 3.3 v
r5 1 1 2 s no.ea - 406 - 160420 24 v set = 5.0 v
r5 1 1 2 s no.ea - 406 - 160420 25 13) power - on transient response (ta = 25 c ) v set = 1.8 v v set = 2.5 v v set = 3.3 v v set = 5.0 v 14) load dump (ta = 25 c ) v set = 1.8 v v set = 2.5 v -100 0 100 200 300 400 500 600 700 800 900 -5 -4 -3 -2 -1 0 1 2 3 4 5 -0.2 0.2 0.6 1 1.4 1.8 inrush current(ma) input voltag(v) / output voltage(v) time(ms) vin cout=0.1(uf) vout cout=10.0(uf) vout cout=0.1(uf) inrush cout=10.0(uf) inrush -100 0 100 200 300 400 500 600 700 800 900 -5 -4 -3 -2 -1 0 1 2 3 4 5 -0.2 0.2 0.6 1 1.4 1.8 inrush current(ma) input voltag(v) / output voltage(v) time(ms) vin cout=0.1(uf) vout cout=10.0(uf) vout cout=0.1(uf) inrush cout=10.0(uf) inrush -100 0 100 200 300 400 500 600 700 800 900 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 -0.2 0.2 0.6 1 1.4 1.8 inrush current(ma) input voltag(v) / output voltage(v) time(ms) vin cout=0.1(uf) vout cout=10.0(uf) vout cout=0.1(uf) inrush cout=10.0(uf) inrush -100 0 100 200 300 400 500 600 700 800 900 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 -0.2 0.2 0.6 1 1.4 1.8 inrush current(ma) input voltag(v) / output voltage(v) time(ms) vin cout=0.1(uf) vout cout=10.0(uf) vout cout=0.1(uf) inrush cout=10.0(uf) inrush
r5 1 1 2 s no.ea - 406 - 160420 26 v set = 3.3 v v set = 5.0 v 15) cranking (ta = 25 c ) v set = 5.0 v 16) detect / release delay time vs. temperature detect output delay time release output delay time 0 5 10 15 20 25 -40 -25 -10 5 20 35 50 65 80 95 output delay time for release (s ) ta( c) 0 1 2 3 4 5 6 7 8 -40 -25 -10 5 20 35 50 65 80 95 output delay time for reset ( ms) ta( c)
r5 1 1 2 s no.ea - 406 - 160420 27 17) detect / release delay time vs. input voltage detect output delay time release output delay time 1 8 ) detect (release) delay time vs. external capacit ance for cd pin (ta = 25 c ) 1 9 ) pulse width vs. overdrive voltage (ta = 25 c ) 0 5 10 15 20 25 30 35 0 6 12 18 24 30 36 42 output delay time for release ( s ) input voltage (v) -40(c) 25(c) 105(c) 0 1 2 3 4 5 6 7 8 0 6 12 18 24 30 36 42 output delay time for reset ( ms) input voltage (v) -40(c) 25(c) 105(c) 0 0 1 10 100 1000 0.01 1 100 output delay time for release(ms) output delay time for reset(ms) external capacitance (nf) tdelay tphl 0 50 100 150 200 10 100 1000 pulse width (s) overdrive voltage (mv) vdset=1.6(v) vdset=4.6(v)
r5 1 1 2 s no.ea - 406 - 160420 28 20 ) d out pin voltage vs. sense pin input voltage (ta = 25 c ) - v set = 1.6 v - v set = 2.2 v - v set = 3.0 v - v set = 4.6 v 2 1 ) c d driver output current vs. input voltag e 2 2 ) nch driver output current vs. input voltage ce = 5.0 v, sense = 5.5 v d out = 0.1 v
r5 1 1 2 s no.ea - 406 - 160420 29 2 3 ) d out pin voltage vs. input voltage (v out d etection) (ta = 25 c ) - v set = 1.6 v - v set = 2.2 v - v set = 3.0 v - v set = 4.6 v
r5 1 1 2 s no.ea - 406 - 160420 30 input transient/load transient vs. output c apacity (c2) r5112 performs a stable operation by using 0.1 f of ceramic capacitor as the output capacitor. however, the variation of output voltage may not meet the demand of the system when input voltage and load current vary. in such cases, the variation of output voltage can be minimized significantly by using 1 0 f or higher ceramic capacitor. when using a high - capacity electrolytic capacitor for the output line, place the electrolytic capacitor a few centimeters apart from the ic after arranging the ceramic capacitor close to the ic. input transient response (v set = 3.3 v) load transient response (v set = 3.3 v) 0 2 4 6 8 10 12 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 6.3 6.8 -1 0 1 2 3 4 5 6 input voltage v in (v) output voltage v out (v) time (ms) input voltage tr=tf=1s output voltage i out =1ma c 2 = 0.1f c 2 =10f
r5 1 1 2 s no.ea - 406 - 160420 31 esr vs. o utput current it is recommended that a cerami c type capacitor be used for this device . however, other types of capacitors having lower esr can also be used. the relation between the output current (i out ) and the esr of output capacitor is shown below. r 5112 x xx x b v dd v out ce c 1 c 2 i out c 1 = ceramic 0.1 measurement conditions frequency band : 10 hz to 2 mhz measurement temperature : ? 40c to 125c hatched area : noise level is 4 0 v ( average ) or below ceramic capacitors : c 1 = 0.1 f, c f v set = 1.8 v v set = 2.5 v v set = 3.3 v v set = 5.0 v
power dissipation hsop - 8e ver. a i the p ower d issipation of the package is dependent on pcb material, layout, and environmental conditions. t he following conditions are used in this measurement. measurement conditions ultra - high wattage land pattern environment mounting on board (wind v elocity = 0 m/s) board material glass c loth e poxy p lastic ( four - l ayer board ) board dimensions 76.2 mm 114.3 mm 0.8 mm copper ratio outer layers (first and fourth layers) : approx. 95% of 5 0 mm s quare inner layers (second and third layers) : approx. 100% of 50 mm s quare through - holes 0. 4 mm 21 pcs measurement result (ta = 25 c, tjmax = 1 2 5 c) ultra - high wattage land pattern power dissipation 2.9 w thermal resistance ? ic mount area (mm) p ower dissipation vs. ambient temperature m easurement board pattern power dissipation p d (w) 0 25 50 75 100 125 150 ambient temperature ( c) 4.0 3.0 2.0 1.0 0 105 ultra - high wattage land pattern 2.9
package dimensions hsop-8e i hsop-8e package dimensions ? the tab on the bottom of the package shown by blue circle is substrate potential ( gnd). it is recomm ended that this tab be connected to the ground plane on the board but it is possible to leave the tab floating. ?
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